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may 2008 PCS3P73Z01BW rev 0.2 notice: the information in this document is subject to change without notice. pulsecore semiconductor corporation 1715 s. bascom ave suite 200, campbell, ca 95008 ? tel: 408-879-9077 ? fax: 408-879-9018 www. p ulsecoresemi.com wide frequency range timing-safe? peak emi reduction ic general features ? 1x , lvcmos timing-safe? peak emi reduction ? input frequency: 12mhz - 150mhz @ 2.5v 15mhz - 175mhz @ 3.3v ? output frequency ( timing-safe?): 12mhz - 150mhz @ 2.5v 15mhz - 175mhz @ 3.3v ? analog spread selection up to 1% ? external input-output delay control option ? power down option for power save mode ? supply voltage: 2.5v0.2v 3.3v 0.3v ? commercial temperature range ? 8 pin, tssop, and tdfn(2x2) col packages ? the first true drop-in solution functional description PCS3P73Z01BW is a 2.5v/3.3v versatile emi reduction ic based on pulsecore semiconductor?s patent pending timing-safe? technology. PCS3P73Z01BW accepts one input from an external re ference, and locks on to it delivering a 1x timing-safe? clock. PCS3P73Z01BW has a frequency selection (fs) control that facilitates selecting one of the two frequency ranges within the operating frequency range. refer to the frequency selection table for details . the device has an ssextr pin to select different deviations and associated input-output skew (t skew ), depending upon the value of an external resistor connected between ssextr and gnd. PCS3P73Z01BW has a dly_ctrl for adjusting the input-output clock delay, depending upon the value of capacitor connected at this pin to gnd. pd#/oe provides the power down option. outputs will be tri-stated when power down is active. PCS3P73Z01BW operates from a 2.5v/3.3v supply and is available in an 8 pin tssop, and tdfn (2x2) col packages, over commercial temperature range. application PCS3P73Z01BW is targeted for use in displays, camera modules and high speed sdram memory interface systems. block diagram vdd gnd ssextr clkin modout (timing-safe?) pll fs pd#/oe dly_ctrl
may 2008 PCS3P73Z01BW rev 0.2 wide frequency range timing-safe? peak emi reduction ic 2 of 16 notice: the information in this document is subject to change without notice. ssextr dly_ctrl pin configuration pin description pin # type pin name description 1 i clkin external reference clock input. 2 i pd#/oe power down. pull low to enable power down. outputs will be tri-stated when power down is enabled. pull high to disable power down and enable output. 3 i fs frequency select (see frequency selection table for details). 4 p gnd ground 5 o modout buffered modulated timing-safe? clock output 6 o dly_ctrl external in put-output delay control 7 i ssextr analog spread selection th rough external resistor to gnd. 8 p vdd 2.5v / 3.3v supply voltage frequency selection table vdd fs frequency(mhz) 0 12-40 2.5v 1 40-150 0 15-50 3.3v 1 50-175 absolute maximum rating symbol parameter rating unit v dd voltage on any pin with respect to ground -0.5 to +4.6 v t stg storage temperature -65 to +125 c t s max. soldering temperature (10 sec) 260 c t j junction temperature 150 c t dv static discharge voltage (as per jedec std22- a114-b) 2 kv note: these are stress ratings only and are not implied for functional use. exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. pd#/oe modout clkin 6 1 2 3 4 5 8 gnd fs vdd 7 PCS3P73Z01BW
may 2008 PCS3P73Z01BW rev 0.2 wide frequency range timing-safe? peak emi reduction ic 3 of 16 notice: the information in this document is subject to change without notice. operating conditions parameter description min max unit v dd(3.3v) supply voltage 3.0 3.6 v v dd(2.5v) supply voltage 2.3 2.7 v t a operating temperature (amb ient temperature) 0 +70 c c l load capacitance 10 pf c in input capacitance 7 pf electrical characteristics for 2.5v supply parameter description test conditions min typ max unit v dd supply voltage 2.3 2.5 2.7 v v il input low voltage 0.7 v v ih input high voltage 1.7 v i il input low current v in = 0v 50 a i ih input high current v in = v dd 50 a v ol output low voltage i ol = 8ma 0.6 v v oh output high voltage i oh = -8ma 1.8 v i cc static supply current clkin & pd#/ oe pins pulled to gnd 2 a 12mhz 3 40mhz 7 i dd dynamic supply current unloaded output 150mhz 15 ma z o output impedance 36 ? electrical characteristics for 3.3v supply parameter description test conditions min typ max unit v dd supply voltage 3.0 3.3 3.6 v v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current v in = v dd 50 a i il input low current v in = 0v 50 a v oh output high voltage i oh = -8ma 2.4 v v ol output low voltage i ol =8ma 0.4 v i cc static supply current clkin pulled low, pd#/oe pulled low 2 a 15mhz 5 50mhz 10 i dd dynamic supply current unloaded outputs 175mhz 25 ma z o output impedance 27 ?
may 2008 PCS3P73Z01BW rev 0.2 wide frequency range timing-safe? peak emi reduction ic 4 of 16 notice: the information in this document is subject to change without notice. switching characteristics for 2.5v parameter test conditions min typ max unit fs=0 12 40 input frequency fs=1 40 150 fs=0 12 40 modout fs=1 40 150 mhz 100mhz 45 50 55 duty cycle 1, 2 measured at v dd /2 100mhz 40 50 60 % rise time 1, 2 measured between 20% to 80% 1.7 ns fall time 1, 2 measured between 80% to 20% 0.9 ns fs=0; @ 25 mhz 175 cycle-to-cycle jitter 2 unloaded outputs fs=1; @ 66 mhz 150 ps fs=0; @ 25 mhz input-to-output propagation delay 2 unloaded outputs with ssextr pin open, no load on dly_ctrl fs=1; @ 66 mhz 250 ps pll lock time 2 stable power supply, valid clock presented on clkin pin 3 ms notes: 1. all parameters are specified with 10 pf loaded outputs. 2. parameter is guaranteed by design and characterization. not 100% tested in production switching characteristics for 3.3v parameter test conditions min typ max unit fs=0 15 50 input frequency fs=1 50 175 fs=0 15 50 modout fs=1 50 175 mhz 100mhz 45 50 55 duty cycle 3,4 measured at v dd /2 100mhz 40 50 60 % rise time 3,4 measured between 20% to 80% 1.2 ns fall time 3,4 measured between 80% to 20% 0.8 ns fs=0; @ 25 mhz 150 cycle-to-cyclejjitter 4 unloaded outputs fs=1; @ 66 mhz 125 ps fs=0; @ 25 mhz input-to-output propagation delay 4 unloaded outputs with ssextr pin open, no load on dly_ctrl fs=1; @ 66 mhz 350 ps pll lock time 4 stable power supply, valid clock presented on clkin pin 3 ms notes: 3. all parameters are specified with 10 pf loaded outputs. 4. parameter is guaranteed by design and characterization. not 100% tested in production
may 2008 PCS3P73Z01BW rev 0.2 wide frequency range timing-safe? peak emi reduction ic 5 of 16 notice: the information in this document is subject to change without notice. switching waveforms duty cycle timing all outputs rise/fall time input - output propagation delay input-output skew t 2 t 1 v dd /2 v dd /2 v dd /2 output t 3 output 0v t 4 3.3v 20% 80% 20% 80% t 6 output input v dd /2 v dd /2 t skew represents input-output skew when spread spectrum is on for example, t skew = 0.20 for an input clock of 12mhz, translates in to (1/12mhz) * 0.20=16.66ns t skew - one clock cycle n=1 t skew + input timing-safe? output note: tskew is measured in units of clock period
may 2008 PCS3P73Z01BW rev 0.2 wide frequency range timing-safe? peak emi reduction ic 6 of 16 notice: the information in this document is subject to change without notice. typical example of timing-safe? waveform typical application schematic input input modout with ssoff timing-safe? modout external spread control vdd external input-output delay control 0 ? 0 ? clkin pd#/oe ssextr modout fs gnd 1 2 3 4 5 7 8 vdd dly_ctrl 6 clkin 0.01uf vdd note: refer to pin description table for functionality details 0 ? 0 ? vdd r c ssextr can be pulled high to turn off ss
may 2008 PCS3P73Z01BW rev 0.2 wide frequency range timing-safe? peak emi reduction ic 7 of 16 notice: the information in this document is subject to change without notice. charts (for vdd=2.5v0.2v) deviation vs resistance 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 100 200 300 400 500 600 700 800 resistance (kohms) deviation (+/-) 12mhz fig1: deviation vs resistance (12mhz, fs=0) charts (for vdd=2.5v0.2v and 3.3v0.3v) tskew vs resistance 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25 100 200 300 400 500 600 700 800 resistance (kohms) tskew 12mhz fig2: tskew vs resistance (12mhz, fs=0) deviation vs resistance 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 40 50 60 70 80 90 100 110 120 130 140 150 160 resistance (kohms) deviation (+/-) 25mhz tskew vs resistance 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25 40 50 60 70 80 90 100 110 120 130 140 150 160 resistance (kohms) tskew 25mhz fig3: deviation vs resistance (25mhz, fs=0) fig4: tskew vs resistance (25mhz, fs=0) deviation vs resistance 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 30 40 50 60 70 80 90 100 110 120 130 140 150 resistance (kohms) deviation (+/-) 33mhz fig5: deviat ion vs resistance (33mhz, fs=0) tskew vs resistance 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25 30 40 50 60 70 80 90 100 110 120 130 140 150 resistance (kohms) tskew 33mhz fig6: tskew vs resistance (33mhz, fs=0)
may 2008 PCS3P73Z01BW rev 0.2 wide frequency range timing-safe? peak emi reduction ic 8 of 16 notice: the information in this document is subject to change without notice. deviation vs resistance 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 30 40 50 60 70 80 90 100 110 120 resistance (kohms) deviation (+/-) 40mhz fig7: deviation vs resistance (40mhz, fs=0) deviation vs resistance 0.05 0.1 0.15 0.2 0.25 250 300 350 400 450 500 550 600 650 700 750 800 850 900 resistance (kohms) deviation (+/-) 66mhz tskew vs resistance 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25 30 40 50 60 70 80 90 100 110 120 resistance (kohms) tskew 40mhz fig8: tskew vs resistance (40mhz, fs=0) tskew vs resistance 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25 250 300 350 400 450 500 550 600 650 700 750 800 850 900 resistance (kohms) tskew 66mhz deviation vs resistance 0.05 0.1 0.15 0.2 0.25 0.3 150 180 210 240 270 300 330 resistance (kohms) deviation (+/-) 75mhz tskew vs resistance 0.1 0.125 0.15 0.175 0.2 0.225 0.25 150 180 210 240 270 300 330 resistance (kohms) tskew 75mhz fig9: deviation vs resistance (66mhz, fs=1) fig10: tskew vs resistance (66mhz, fs=1) fig11: deviation vs resistance (75mhz, fs=1) fig12: tskew vs resistance (75mhz, fs=1)
may 2008 PCS3P73Z01BW rev 0.2 wide frequency range timing-safe? peak emi reduction ic 9 of 16 notice: the information in this document is subject to change without notice. deviation vs resistance 0.05 0.1 0.15 0.2 0.25 0.3 120 150 180 210 240 270 300 resistance (kohms) deviation (+/-) 100mhz tskew vs resistance 0.1 0.125 0.15 0.175 0.2 0.225 0.25 120 150 180 210 240 270 300 resistance (kohms) tskew 100mhz fig13: deviation vs resistance (100mhz, fs=1) deviation vs resistance 0.05 0.1 0.15 0.2 0.25 0.3 80 110 140 170 200 230 260 290 resistance (kohms) deviation (+/-) 133mhz fig15: deviation vs resistance (133mhz, fs=1) fig14: tskew vs resistance (100mhz, fs=1) tskew vs resistance 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25 80 110 140 170 200 230 260 290 resistance (kohms) tskew 133mhz fig16: tskew vs resistance (133mhz, fs=1) deviation vs resistance 0.05 0.1 0.15 0.2 0.25 0.3 60 90 120 150 180 210 240 270 resistance (kohms) deviation (+/-) 150mhz fig17: deviation vs resistance (150mhz, fs=1) tskew vs resistance 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25 60 90 120 150 180 210 240 270 resistance (kohms) tskew 150mhz fig18 : tskew vs resistance (150mhz, fs=1)
may 2008 PCS3P73Z01BW rev 0.2 wide frequency range timing-safe? peak emi reduction ic 10 of 16 notice: the information in this document is subject to change without notice. charts (for vdd= 3.3v0.3v) deviation vs resistance 0.05 0.1 0.15 0.2 0.25 0.3 50 60 70 80 90 100 110 120 130 140 150 160 170 180 resistance (kohms) deviation (+/-) 166mhz fig19: deviation vs resistance (166mhz, fs=1) tskew vs resistance 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25 50 60 70 80 90 100 110 120 130 140 150 160 170 180 resistance (kohms) tskew 166mhz deviation vs resistance 0.05 0.1 0.15 0.2 0.25 0.3 40 50 60 70 80 90 100 110 120 130 140 150 160 resistance (kohms) deviation (+/-) 175mhz fig21: deviation vs resistance (175mhz, fs=1) tskew vs resistance 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25 40 50 60 70 80 90 100 110 120 130 140 150 160 resistance (kohms) tskew 175mhz fig20: tskew vs resistance (166mhz, fs=1) fig22: tskew vs resistance (175mhz, fs=1)
may 2008 PCS3P73Z01BW rev 0.2 wide frequency range timing-safe? peak emi reduction ic 11 of 16 notice: the information in this document is subject to change without notice. charts (for vdd=2.5v0.2v) i/o delay vs load (dly_ctrl) -600 -400 -200 0 200 400 600 800 0123456789101112131415 capacitance (pf) i/o delay (ns) 2.3v 2.5v 2.7v 3v 3.3v 3.6v fig23: i/o delay vs load (dly_ctrl) (for 12mhz, fs=0) charts (for vdd=2.5v0.2v and 3.3v0.3v) i/o delay vs load (dly_ctrl) -800 -600 -400 -200 0 200 400 600 800 0123456789101112131415 capacitance (pf) i/o delay (ns) 2.3v 2.5v 2.7v 3v 3.3v 3.6v i/o delay vs load (dly_ctrl) -800 -600 -400 -200 0 200 400 600 800 0123456789101112131415 capacitance (pf) i/o delay (ns) 2.3v 2.5v 2.7v 3v 3.3v 3.6v fig24: i/ o delay vs load (dly_ctrl) (for 25mhz, fs=0) i/o delay vs load (dly_ctrl) -1000 -800 -600 -400 -200 0 200 400 600 800 0 1 2 3 4 5 6 7 8 9 101112131415 capacitance (pf) i/o delay (ns) 2.3v 2.5v 2.7v 3v 3.3v 3.6v i/o delay vs load (dly_ctrl) -800 -600 -400 -200 0 200 400 600 800 0123456789101112131415 capacitance (pf) i/o delay (ns) 2.3v 2.5v 2.7v 3v 3.3v 3.6v fig25: i/o delay vs load (dly_ctrl) ( for 33mhz , fs=0 ) fig26: i/o delay vs load (dly_ctrl) ( for 40mhz , fs=0 ) fig27: i/o delay vs load (dly_ctrl) ( for 66mhz , fs=1 )
may 2008 PCS3P73Z01BW rev 0.2 wide frequency range timing-safe? peak emi reduction ic 12 of 16 notice: the information in this document is subject to change without notice. i/o delay vs load (dly_ctrl) -1000 -800 -600 -400 -200 0 200 400 600 800 0 1 2 3 4 5 6 7 8 9 101112131415 capacitance (pf) i/o delay (ns) 2.3v 2.5v 2.7v 3v 3.3v 3.6v i/o delay vs load (dly_ctrl) -1000 -800 -600 -400 -200 0 200 400 600 800 0 1 2 3 4 5 6 7 8 9 101112131415 capacitance (pf) i/o delay (ns) 2.3v 2.5v 2.7v 3v 3.3v 3.6v charts (for vdd= 3.3v0.3v) i/o delay vs load (dly_ctrl) -600 -400 -200 0 200 400 600 800 0123456789101112131415 capacitance (pf) i/o delay (ns) 3v 3.3v 3.6v i/o delay vs load (dly_ctrl) -1000 -800 -600 -400 -200 0 200 400 600 800 0 1 2 3 4 5 6 7 8 9 101112131415 capacitance (pf) i/o delay (ns) 2.3v 2.5v 2.7v 3v 3.3v 3.6v i/o delay vs load (dly_ctrl) -1000 -800 -600 -400 -200 0 200 400 600 800 0 1 2 3 4 5 6 7 8 9 101112131415 capacitance (pf) i/o delay (ns) 2.3v 2.5v 2.7v 3v 3.3v 3.6v i/o delay vs load (dly_ctrl) -800 -600 -400 -200 0 200 400 600 800 0123456789101112131415 capacitance (pf) i/o delay (ns) 3v 3.3v 3.6v fig28: i/o delay vs load (dly_ctrl) ( for 75mhz , fs=1 ) fig29: i/o delay vs load (dly_ctrl) ( for 100mhz , fs=1 ) fig30: i/o delay vs load (dly_ctrl) ( for 133mhz , fs=1 ) fig31: i/o delay vs load (dly_ctrl) ( for 150mhz , fs=1 ) fig32: i/o delay vs load (dly_ctrl) ( for 166mhz , fs=1 ) fig33: i/o delay vs load (dly_ctrl) ( for 175mhz , fs=1 ) note: device to device variation of deviation and i/o delay is 10%
may 2008 PCS3P73Z01BW rev 0.2 wide frequency range timing-safe? peak emi reduction ic 13 of 16 notice: the information in this document is subject to change without notice. e h a a1 a2 d b c l e package information 8-lead tssop package (4.40-mm body) dimensions inches millimeters symbol min max min max a 0.043 1.10 a1 0.002 0.006 0.05 0.15 a2 0.033 0.037 0.85 0.95 b 0.008 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 d 0.114 0.122 2.90 3.10 e 0.169 0.177 4.30 4.50 e 0.026 bsc 0.65 bsc h 0.252 bsc 6.40 bsc l 0.020 0.028 0.50 0.70 0 8 0 8
may 2008 PCS3P73Z01BW rev 0.2 wide frequency range timing-safe? peak emi reduction ic 14 of 16 notice: the information in this document is subject to change without notice. tdfn col 2x2 8l package outline drawing dimensions inches millimeters symbol min max min max a 0.027 0.0315 0.70 0.80 a3 0.008 bsc 0.203 bsc b 0.008 0.012 0.20 0.30 d 0.079 bsc 2.00 bsc e 0.078 bsc 2.00 bsc e 0.020 bsc 0.50 bsc l 0.020 0.024 0.50 0.60
may 2008 PCS3P73Z01BW rev 0.2 wide frequency range timing-safe? peak emi reduction ic 15 of 16 notice: the information in this document is subject to change without notice. ordering codes ordering code marking package type temperature PCS3P73Z01BWg-08-tt 3p73z01bwg 8-pin 4.4-mm tssop - tube, green commercial PCS3P73Z01BWg-08-tr 3p73z01bwg 8- pin 4.4-mm tssop - tape & reel, green commercial PCS3P73Z01BWg-08-cr af1ll 8- pin 2-mm tdfn col - tape & reel, green commercial ll = 2 character lot # device ordering information PCS3P73Z01BWg-08-tr o = tsot23 u = msop j=tsot26 s = soic e = tqfp c=tdfn (2x2) col t = tssop l = lqfp a = ssop u = msop v = tvsop p = pdip b = bga d = qsop q = qfn x = sc - 70 device pin count x= automotive i= industrial p or n/c = commercial (-40c to +125c) (-40c to +85c) (0c to +70c) 1 = reserved 6 = power management 2 = non pll based 7 = power management 3 = emi reduction 8 = power management 4 = ddr support products 9 = hi performance 5 = std zero dela y buffe r 0 = reserved pulsecore semiconductor mixed signal product part number f = lead free and rohs compliant part g = green package, lead free, and rohs r = tape & reel, t = tube or tray
may 2008 PCS3P73Z01BW rev 0.2 wide frequency range timing-safe? peak emi reduction ic 16 of 16 notice: the information in this document is subject to change without notice. ? copyright 2006 pulsecore semiconductor co rporation. all rights reserved. our logo and name are trademarks or registered trade marks of pulsecore semiconductor. all other brand and product names may be t he trademarks of their respective companies. pulsecore reser ves the right to make changes to this document and its products at any time without notice. pulsecore assumes no responsibility for any errors that may appear in this document. the data contained herein represents pu lsecore?s best data and/or estimates at the time of issuanc e. pulsecore reserves the right to change or correct this data at any time, without notice. if the product described herein is und er development, significant changes to these specificati ons are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. pulsecore does not assume any responsibility or liab ility arising out of the application or use of any product descri bed herein, and disclaims any express or implied warranties related to the sale and/or use of pulsecore produc ts including liability or warrant ies related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agree d to in pulsecore?s terms and conditions of sale (which are available from pulsecor e). all sales of pulsecore produc ts are made exclusively accordi ng to pulsecore?s terms and conditions of sale. the purchase of produc ts from pulsecore does not c onvey a license under any patent ri ghts, copyrights; mask works rights, trademarks, or any other intellect ual property rights of pulsecore or third parties. pulsecore d oes not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of pulsecore products in such lif e-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify pu lsecore against all claims arising from such use. pulsecore semiconductor corporation 1715 s. bascom ave suite 200, campbell, ca 95008 tel: 408-879-9077 fax: 408-879-9018 www.pulsecoresemi.com copyright ? pulsecore semiconductor all rights reserved part number: PCS3P73Z01BW document version: 0.2 note: this product utilizes us patent # 6,646,463 impedance emulator patent issued to pulsecore semiconductor, dated 11-11-2003 many pulsecore semiconductor products are pr otected by issued patents or by applications for patent

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